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ssrs 2d barcode IMPLEMENTATION O F DISCRETETIME SYSTEMS in Software
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Structures for FIR Systems
Find the frequency response of the system defined by the following network: CHAP. 81
IMPLEMENTATION O F DISCRETETIME SYSTEMS
We recognize this structure as a linear phase system with a unit sample response h ( n ) = O.I[S(n) + 6(n  6)1 + 0.2[6(n I ) + 6(n  5 ) ].t0.5[6(n 2) + 6(n  4)] + 6(n  3 ) A linear shiftinvariant system has a unit sample response given by
h(0) = 0.01 / (I)= 0.02 h(2) = 0.10 h(3) = h(5) = 0.40 0.02 h(4) = 0.10 h(6) = 0.01 (a) Draw a signal flowgraph for this system that requires the minimum number of multiplications. (b) If the input to this system is bounded with Ix(n)l 4 I for all n , what is the maximum value that the output. y(n ), can attain (a) Because this system is a linear phase filter, it may be implemented with a network that has only four multiplies and six delays as shown in the figure below. ( b ) With an input x i n ) , the output is
Therefore, the magnitude of y(n) is upper bounded by
With Ix(n)l < 1 for all n, IMPLEMENTATION OF DISCRETETIME SYSTEMS
[CHAP. 8
The unit sample response of an FIR filter is
h(n) = otherwise
(a) Draw the direct form implementation of this system.
(b) Show that the corresponding system function is
and use this to draw a flowgraph that is a cascade of an FIR system with an IIR system
(c) For both of these implementations, determine the number of multiplications and additions required to compute each output value and the number of storage registers that are required. (a) With a unit sample response
h(n) = an[u(n)  u(n  7)] the direct form implementation of this system is as shown below.
(b) The system function is
which converges for Izl z 0. Thus, H ( z ) may be implemented as a cascade of an IIR system, with an FIR system, H2(z)= 1  u7z' Therefore, an alternative implementation of this system is as shown below.
where the branch labeled with z6 represents a delay by 6.
(c) The direct form structure requires six delays, which is the minimum number necessary for this system, six multiplications, and six additions. The cascade, on the other hand, requires one additional delay but only two multiplications and two additions. A DSP chip used in realtime signal processing applications has an instruction cycle time of 100 ns. One of the instructions in the instruction set, MACD, will fetch a value from data memory (input signal), fetch another data value from program memory (filter coefficient), multiply the two numbers together, add the product to the accumulator, and then move a number in data memory into the next memory location (this corresponds to a shift or delay of the data sequence). Thus, for an FIR filter of order N, to find the value CHAP. 81
IMPLEMENTATION OF DISCRETETIME SYSTEMS
of the output at time n , we need one instruction to read the new input value, x ( n ) , into the processor, we need (N 1) MACD instructions to evaluate the sum and we need one instruction to output the value of y(n). In addition, there are eight other instruction cycles required for each n in order to perform such functions as setting up memory pointers, zeroing the accumulator, and so on. (a) With these requirements in mind, determine the maximum bandwidth signal that may be filtered with an FIR filter of order N = 255, in real time, using a single DSP chip. (b) A speech waveform x , ( t ) is sampled at 8 kHz. Determine the maximum length FIR filter that may be used to filter the sampled speech signal in real time. (a) For the given DSP chip, we need N 1 I instruction cycles to compute a single output value for an FIR filter of order N. Therefore, with N = 255, we need 266 cycles, or 266 x s to compute each output point. Thus, the signal to be filtered cannot be sampled any faster than = 266 x

