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_ C(log V1 + log V2) + V1V2
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Fig. 9-26
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Since xy eln x ln y , the circuit of Fig. 9-26 is a possible realization.
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Two identical passive RC low-pass lter sections are to be connected in cascade so as to create a double-pole lter with corner frequency at 1= 1=RC. (a) Will simple cascade connection of these lters yield the desired transfer function T s 1= 2 = s 1= 2 (b) If not, how may the desired result be realized
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(a) With simple cascading, the overall transfer function would be Vo 1= 2 T0 2 Vi s 3 1= s 1= 2 which has two distinct negative roots. The desired result is not obtained because the impedance looking into the second stage is not in nite, and thus, the transfer function of the rst stage is not simply 1= = s 1= . (b) The desired result can be obtained by adding a unity follower (Fig. 9-13) between stages (see Problem 9.44), as illustrated in Fig. 9-27.
R + _ C C +
Fig. 9-27
(a) Find the transfer function for the circuit of Fig. 9-28. (b) In control theory, there is a compensation network whose transfer function is of the form s 1=1 = s 1=2 ; it is called a lead-lag network if 1=1 < 1=2 , and a lag-lead network if 1=2 < 1=1 . Explain how the circuit of Fig. 9-28 may be used as such a compensation network.
OPERATIONAL AMPLIFIERS
[CHAP. 9
(a) By extension of (9.5), R2 Vo Z2 C s 1=1 sR2 C2 1 T s 1 R1 VS Z1 C2 s 1=2 sR1 C1 1 where 1 R1 C1 and 2 R2 C2 . (b) To obtain unity gain, set C1 C2 . To obtain a positive transfer function, insert an inverter stage either before or after the circuit. Then, the selection of R1 > R2 yields 1=1 < 1=2 , giving the lead-lag network, and R1 < R2 results in 1=2 < 1=1 , giving the lag-lead network.
R2 R R1 1 +
R 3 +
C1 0
+ R i2
Fig. 9-28
Fig. 9-29
Show that the transfer function for the op amp circuit of Fig. 9-29 is vo =vi 1.
Because the op amp draws negligible current, i2 0. v1 % v2 vi and i1 Also, by the method of node voltages, i1 Thus, vi vo and so vo =vi 1. vi vo 0 2R vi v1 %0 R Hence, v2 vi . However, since vd % 0,
Use an op amp to design a noninverting voltage source (see Problem 9.9). conditions under which regulation is maintained in your source.
Determine the
Simply replace the inverting ampli er of Fig. 9-17 with the noninverting ampli er of Fig. 9-3. Since the op amp draws negligible current, regulation is preserved if VS and RS are selected so that iZ remains within the regulation range of the Zener diode. Speci cally, regulation is maintained if 0:1IZ VS =RS IZ .
For the noninverting ampli er of Fig. 9-3: (a) Compare the expressions obtained for voltage gain with common-mode rejection (Example 9.4) and without (in the ideal ampli er of Example 9.3), for AOL ! 1. (b) Show that if CMRR is very large, then it need not be considered in computing the gain.
CHAP. 9]
OPERATIONAL AMPLIFIERS
(a) We let AOL ! 1 in (9.13), since that is implicit in Example 9.3:   AOL AOL =CMRR lim Av lim AOL ! 1 AOL ! 1 1 AOL R1 = R1 R2 1 AOL R1 = R1 R2   R2 1 R2 1 1 R1 CMRR R1
Now we can compare (1) above with (9.7); the di erence is the last term on the right-hand side of (1) above. (b) Let CMRR ! 1 in (1) above to get lim Av 1 R2 R1
CMRR!1 AOL ! 1
which is identical to the ideal case of Example 9.3.
The ampli er of Fig. 9-9 has been shown in Example 9.10 to be a signal-conditioning ampli er with gain sensitive to the polarity of vS . Use SPICE methods to simulate this ampli er if R1 10 k and R2 R3 20 k. Use the op amp model of Section 9.12. The ideal diode can be realized by specifying the emission coe cient n 1 10 10 . Use the simulation results to validate (9.21) and (9.22).
The netlist code that describes the circuit is as follows:
Prb9_25.CIR vs 1 0 SIN( 0V 0.5V 1000Hz ) R1 1 2 10kohm R2 2 4 20kohm D2 4 3 DMOD R3 2 3 20kohm X1 2 0 3 0 OPAMP .SUBCKT OPAMP 1 2 3 4 * Model Inv NInv Out Com Rd 1 2 500kohm E 5 4 (1,2) -le5 Ro 5 3 100ohm .ENDS OPAMP .MODEL DMOD D(n=le-10) ; Ideal diode .TRAN 1us 2ms .PROBE .END
Execute hPrb9_25.CIRi and use the Probe feature of PSpice to yield Fig. 9-30 where it is seen that for vS > 0, Av 0:5=0:5 1. By (9.21), the predicted gain is Av R2 R3 20 103 20 103 1 R1 R2 R3 10 103 20 103 20 103 By (9.22), the expected gain is
Thus, (9.21) is validated. From Fig. 9-30 for vS < 0, Av 1=0:5 2. Av Hence, (9.22) is also validated.
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