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JFET TERMINAL CHARACTERISTICS
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The JFET is almost universally applied in the common-source (CS) two-port arrangement of Fig. 4-1, where vGS maintains a reverse bias of the gate-source pn junction. The resulting gate leakage current is negligibly small for most analyses (usually less than 1 A), allowing the gate to be treated as an open circuit. Thus, no input characteristic curves are necessary. Typical output or drain characteristics for an n-channel JFET in CS connection with vGS 0 are given in Fig. 4-2(a). For a constant value of vGS , the JFET acts as a linear resistive device (in the ohmic region) until the depletion region of the reverse-biased gate-source junction extends the width of the channel (a condition called pincho ). Above pincho but below avalanche breakdown, drain current iD 103
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CHARACTERISTICS OF FIELD-EFFECT TRANSISTORS AND TRIODES
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[CHAP. 4
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Drain (D) n Gate (G)
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Depletion region iD G + _ VDD +
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LDS _
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_ VGG + Source (S) (a) n-channel JFET
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D D p iD _ G n n _ VDD + + VGG _
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S (b) p-channel JFET
Fig. 4-1
remains nearly constant as vDS is increased. For speci cation purposes, the shorted-gate parameters IDSS and Vp0 are de ned as indicated in Fig. 4-2(a); typically, Vp0 is between 4 and 5 V. As gate potential decreases, the pincho voltage, that is, the source-to-drain voltage Vp at which pincho occurs, also decreases, approximately obeying the equation Vp Vp0 vGS 4:1
Table 4-1 JFET source S drain D gate G drain supply VDD gate supply VGG drain current iD BJT emitter E collector C base B collector supply VCC base supply VBB collector current iC
CHAP. 4]
CHARACTERISTICS OF FIELD-EFFECT TRANSISTORS AND TRIODES
iD IDSS = Ip0 VDD RS + RD Ohmic region
LGS = 0 V LDS > Vp0
Pinchoff region _1
IDSS
Q DC load line
_2 = V _3 _4 _5
1 RS Q IDQ Transfer bias line
VDSQ
VDD LDS, V
_V p0
VGSQ
Vp0 (a) Drain characteristics (b) Transfer characteristic
Fig. 4-2 CS n-channel JFET
The drain current shows an approximate square-law dependence on source-to-gate voltage for constant values of vDS in the pincho region:  2 v 4:2 iD IDSS 1 GS Vp0 This accounts for the unequal vertical spacing of the characteristic curves in Fig. 4-2(a). Figure 4-2(b) is the graph of (4.2), known as the transfer characteristic and utilized in bias determination. The transfer characteristic is also determined by the intersections of the drain characteristics with a xed vertical line, vDS constant. To the extent that the drain characteristics actually are horizontal in the pincho region, one and the same transfer characteristic will be found for all vDS > Vp0 . (See Fig. 4-4 for a slightly nonideal case.)
JFET SPICE MODEL
The element speci cation statement for a JFET must explicitly assign a model name that is an arbitrary selection of alpha and numeric characters. The general form is J n1 n2 n3 model name Nodes n1 ; n2 , and n3 belong to the drain, gate, and source, respectively. Only the n-channel JFET is addressed in this book. Positive voltage and current directions for the device are clari ed by Fig. 4-3.
Fig. 4-3
CHARACTERISTICS OF FIELD-EFFECT TRANSISTORS AND TRIODES
[CHAP. 4
A .MODEL control statement must appear in the netlist code for a JFET circuit. statement has the following format: .MODEL model name NJF (parameters)
The control
If the parameter eld is left blank, default values are assigned. Nondefault parameters are entered in the parameter eld using the format parameter name value. The speci c parameters of concern in the book are documented by Table 4-2. The SPICE model describes the JFET in the pincho region by iD IDSS Vto vGS 2 Beta Vto vGS 2 Vto 2
Table 4-2 Parameter Vto Beta Rd Rs CGS CGD Description pincho voltage transcond. coe . drain resistance source resistance gate-source cap. gate-drain cap. Major Impact shorted-gate current shorted-gate current current limit current limit high frequency high frequency Default 2 0.0001 0 0 0 0 Units V A/V2   F F
Example 4.1. Use SPICE methods to generate (a) the CS drain characteristics and (b) the transfer characteristic for an n-channel JFET that has the parameter values Vto 4 V, Beta 0:0005 A=V2 , Rd 1 ; Rs 1 , and CGS CGD 2 pF: (a) Figure 4-4(a) shows a connection method for measurement of both the drain characteristics and the transfer characteristic. The following netlist code generates the drain characteristics that have been plotted using the Probe feature of PSpice as Fig. 4-4(b).
Ex4_1a.CIR - JFET drain characteristics vGS 1 0 0V vDS 2 0 0V J 2 1 0 NJFET .MODEL NJFET NJF ( Vto=-4V Beta=0.0005ApVsq + Rd=1ohm Rs=1ohm CGS=2pF CGD=2pF) .DC vDS 0V 25V 0.5V vGS 0V -4V 0.5V .PROBE .END
(b) The netlist code below holds vDS constant to calculate the transfer characteristic that has been plotted by use of the Probe feature as Fig. 4-4(c).
Ex4_1b.CIR - JFET transfer characteristic vGS 1 0 0V vDS 2 0 10V J 2 1 0 NJFET .MODEL NJFET NJF ( Vto=-4V Beta=0.0005ApVsq + Rd=1ohm Rs=1ohm CGS=2pF CGD=2pF) .DC vGS 0V -4V 0.5V .PROBE .END
CHAP. 4]
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