display barcode in ssrs report CHARACTERISTICS OF FIELD-EFFECT TRANSISTORS AND TRIODES in Software

Generation Code39 in Software CHARACTERISTICS OF FIELD-EFFECT TRANSISTORS AND TRIODES

Fig. 4-4

The commonly used voltage-divider bias arrangement of Fig. 4-5(a) can be reduced to its equivalent in Fig. 4-5(b), where the Thevenin parameters are given by RG R1 R2 R1 R2 and VGG R1 V R1 R2 DD 4:3

+ R1 S + RS CS _

0 (a) (b)

Fig. 4-5

With iG 0, application of KVL around the gate-source loop of Fig. 4-5(b) yields the equation of the transfer bias line, iD VGG vGS RS RS 4:4

which can be solved simultaneously with (4.2) or plotted as indicated on Fig. 4-2(b) to yield IDQ and VGSQ , two of the necessary three quiescent variables. Application of KVL around the drain-source loop of Fig. 4-5(b) leads to the equation of the dc load line, iD VDD vDS RS RD RS RD 4:5

which, when plotted on the drain characteristics of Fig. 4-2(a), yields the remaining quiescent value, VDSQ . Alternatively, with IDQ already determined, VDSQ VDD RS RD IDQ

Example 4.2. In the ampli er of Fig. 4-5(a), VDD 20 V; R1 1 M; R2 15:7 M; RD 3 k, and RS 2 k. If the JFET characteristics are given by Fig. 4-6, nd (a) IDQ , (b) VGSQ , and (c) VDSQ . (a) By (4.3), VGG R1 1 106 VDD 20 1:2 V R1 R2 16:7 106

On Fig. 4-6(a), we construct the transfer bias line (4.4); it intersects the transfer characteristic at the Q point, giving IDQ 1:5 mA. (b) The Q point of Fig. 4-6(a) also gives VGSQ 2 V. (c) We construct the dc load line on the drain characteristics, making use of the vDS intercept of VDD 20 V and the iD intercept of VDD = RS RD 4 mA. The Q point was established at IDQ 1:5 mA in part a and at VGSQ 2 V in part b; its abscissa is VDSQ 12:5 V. Analytically, VDSQ VDD RS RD IDQ 20 5 103 1:5 10 3 12:5 V

CHAP. 4]

1 2000

1 1.2

VGSQ (a)

gs ,

_ 1. 0

a _2 Q b _3 _4

20 25

0 1 _ 1.1 0 5 10

_ 5.2

t (b)

Fig. 4-6

As is done in BJT circuits (Section 3.7), coupling (or blocking) capacitors are introduced to con ne dc quantities to the JFET and its bias circuitry. Further, bypass capacitors CS e ectively remove the gain-reducing source resistor insofar as ac signals are concerned, while allowing RS to be utilized in favorably setting the gate-source bias voltage; consequently, an ac load line is introduced with analysis techniques analogous to those of Section 3.7. Graphical analysis is favored for large-ac-signal conditions in the JFET, since the square-law relationship between vGS and iD leads to signal distortion.

Example 4.3. For the ampli er of Example 4.2, let vi sin t ! 1 rad=s and CS ! 1. Graphically determine vds and id . Since CS appears as a short to ac signals, an ac load line must be added to Fig. 4-6(b), passing through the Q point and intersecting the vDS axis at VDSQ IDQ Rac 12:5 1:5 3 17 V We next construct an auxiliary time axis through Q, perpendicular to the ac load line, for the purpose of showing, on additional auxiliary axes as constructed in Fig. 4-6(b), the excursions of id and vds as vgs vi swings 1 V along the ac load line. Note the distortion in both signals, introduced by the square-law behavior of the JFET characteristics.

The n-channel MOSFET (Fig. 4-7) has only a single p region (called the substrate), one side of which acts as a conducting channel. A metallic gate is separated from the conducting channel by an insulating metal oxide (usually SiO2 ), whence the name insulated-gate FET (IGFET) for the device. The p-channel MOSFET, formed by interchanging p and n semiconductor materials, is described by complementary voltages and currents.

Metal oxide Metal Gate (G ) ~ p Drain (D) n+ Enhanced channel Substrate (B)