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The n-channel JFET circuit of Fig. 4-19 employs one of several methods of self-bias. (a) Assume negligible gate leakage current (iG % 0), and show that if VDD > 0, then VGSQ < 0, and hence the device is properly biased. (b) If RD 3 k; RS 1 k; VDD 15 V, and VDSQ 7 V, nd IDQ and VGSQ .
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VDD RD
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Fig. 4-19 (a) By KVL, IDQ VDD VDSQ RS RD 1
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Now VDSQ < VDD , so it is apparent that IDQ > 0. Since iG % 0, KVL around the gate-source loop gives VGSQ IDQ RS < 0 (b) By (1), IDQ and (2), VGSQ 2 10 3 1 103 2 V 15 7 2 mA 3 103 1 103 2
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The n-channel JFET of Fig. 4-20 is characterized by IDSS 5 mA and Vp0 3 V. Let RD 3 k; RS 8 k; VDD 15 V, and VSS 8 V. Find VGSQ and V0 (a) if VG 0 and (b) if VG 10 V.
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VDD RD + + + VG RS VSS _ Vo _ _ V1
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Fig. 4-20
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[CHAP. 4
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(a) Applying KVL around the gate-source loop yields VG VGSQ RS IDQ VSS Solving (1) for IDQ and equating the result to the right side of (4.2) gives   VG VGSQ VSS VGSQ 2 IDSS 1 RS Vp0 Rearranging (2) leads to the following quadratic in VGSQ :
2 VGSQ Vp0 2 Vp0 2IDSS RS Vp0 VGSQ I R VG VSS 0 IDSS RS IDSS RS DSS S
Substituting known values into (3) and solving for VGSQ with the quadratic formula lead to
2 VGSQ 3
3 2 5 10 3 8 10 3 3 2 VGSQ 5 10 3 8 103 0 8 0 5 10 3 8 103 5 10 3 8 103
2 VGSQ 6:225VGSQ 7:2 0
so that
and VGSQ 4:69 V or 1:53 V. Since VGSQ 4:69 V < Vp0 , this value must be considered extraneous as it will result in iD 0. Hence, VGSQ 1:53 V. Now, from (4.2),     VGSQ 2 1:53 2 IDQ IDSS 1 5 10 3 1 1:2 mA 3 Vp0 and, by KVL, V0 IDQ RS VSS 1:2 10 3 8 103 8 1:6 V (b) Substitution of known values into (3) leads to
2 VGSQ 6:225VGSQ 4:95 0
which, after elimination of the extraneous root, results in VGSQ 0:936 V. Then, as in part a,     VGSQ 2 0:936 2 5 10 3 1 2:37 mA IDQ IDSS 1 Vp0 4 and V0 IDQ RS VSS 2:37 10 3 8 103 8 10:96 V
Find the equivalent of the two identical n-channel JFETs connected in parallel in Fig. 4-21.
iD iD1 Q1
D iD2 Q2 G
Fig. 4-21
CHAP. 4]
CHARACTERISTICS OF FIELD-EFFECT TRANSISTORS AND TRIODES
Assume the devices are described by (4.2); then  2  2  2 v v v iD iD1 iD2 IDSS 1 GS IDSS 1 GS 2IDSS 1 GS Vp0 Vp0 Vp0 Because the two devices are identical and connected in parallel, the equivalent JFET has the same pincho voltage as the individual devices. However, it has a value of shorted-gate current IDSS equal to twice that of the individual devices.
The di erential ampli er of Fig. 4-22 includes identical JFETs with IDSS 10 mA and Vp0 4 V. Let VDD 15 V, VSS 5 V, and RS 3 k. If the JFETs are described by (4.2), nd the value of RD required to bias the ampli er such that VDSQ1 VDSQ2 7 V.
7 VDD
RD 2 + 1 +
RD _ 4
Q1 3 +
+ RS RG
iS 6
Fig. 4-22 By symmetry, IDQ1 IDQ2 . KCL at the source node requires that ISQ IDQ1 IDQ2 2IDQ1 With iG1 0, KVL around the left gate-source loop gives VGSQ1 VSS ISQ RS VSS 2IDQ1 RS Solving (4.2) for VGSQ and equating the result to the right side of (2) gives " #  IDQ1 1=2 1 VSS 2IDQ1 RS Vp0 IDSS Rearranging (3) results in a quadratic in IDQ : " #     VSS Vp0 Vp0 2 1 VSS Vp0 2 2 0 IDQ1 IDQ1 RS 2RS IDSS 2RS Substituting known values into (4) yields
2 IDQ1 3:04 10 3 IDQ1 2:25 10 6 0
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