barcode fonts for ssrs a  p 2 Ip R L PLac 10 3 = 2 2 10 103 100% 0:208% 100% 100% 2:4 PPP VPP IP in Software

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a  p 2 Ip R L PLac 10 3 = 2 2 10 103 100% 0:208% 100% 100% 2:4 PPP VPP IP
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(b) Ideally, the input signal could be increased until iP swings 8 mA; thus,  2 8 max 0:208% 13:31% 1
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The triode ampli er of Fig. 4-30 utilizes cathode bias to eliminate the need for a grid power supply. The very large resistance RG provides a path to ground for stray charge collected by the grid; this current is so small, however, that the voltage drop across RG is negligible. It follows that the grid is maintained at a negative bias, so vG RK iP 1
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CC RL RG _ RK CK _ VPP
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Fig. 4-30
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A plot of (1) on the plate characteristics is called the grid bias line, and its intersection with the dc load line determines the Q point. Let RL 11:6 k; RK 400 ; RG 1 M, and VPP 300 V. If the plate characteristics of the triode are given by Fig. 4-31, (a) draw the dc load line, (b) sketch the grid bias line, and (c) determine the Q-point quantities.
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(a) The dc load line has horizontal intercept VPP 300 V and vertical intercept VPP VPP 300 25 mA Rdc RL RK 11:6 0:4 103 as shown on the plate characteristics of Fig. 4-31. (b) Points for the plot of (1) are found by selecting values of iP and calculating the corresponding values of vG . For example, if iP 5 mA, then vG 400 5 10 3 2 V, which plots as point 1 of the dashed grid bias line in Fig. 4-31. Note that this is not a straight line. (c) From the intersection of the grid bias line with the dc load line, IPQ 10 mA; VPQ 180 V, and VGQ 4 V.
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CHAP. 4]
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CHARACTERISTICS OF FIELD-EFFECT TRANSISTORS AND TRIODES
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iP, mA
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LG = 0 V
_2 AC load line _4 _6
_8 DC load line _ 10 _ 12
Q Grid bias line
L P, V
2Vpm
Fig. 4-31
Supplementary Problems
4.28 In the JFET ampli er of Example 4.2, R1 is changed to 2 M to increase the input impedance. If RD , RS , and VDD are unchanged, what value of R2 is needed to maintain the original Q point Ans: 15:67 M Find the voltage across RS in Example 4.2. Ans: 3V Ans: 940 k
4.29 4.30 4.31
Find the input impedance as seen by source vi of Example 4.2 if CC is large.
The method of source bias, illustrated in Fig. 4-32, can be employed for both JFETs and MOSFETs. For a JFET with characteristics given by Fig. 4-6 and with RD 1 k; RS 4 k; and RG 10 M, determine VDD and VSS so that the ampli er has the same quiescent conditions as the ampli er of Example 4.2. Ans: VSS 4 V; VDD 16 V In the drain-feedback-biased ampli er of Fig. 4-9(a), VDD 15 V; RF 5 M; IDQ 0:7 mA, and VGSQ 4:5 V. Find (a) VDSQ and (b) RL . Ans: a 4:5 V; b 14 k A JFET ampli er with the circuit arrangement of Fig. 4-5 is to be manufactured using devices as described in Problem 4.7. For the design, assume a nominal device and use VDD 24 V; VDSQ 15 V; IDQ 2 mA, R1 2 M, and R2 30 M. (a) Determine the values of RS and RD for the ampli er. (b) Predict the range of IDQ that can be expected. Ans: a RS 1:475 k; RD 3:03 k; b 1:8 to 2.2 mA To see the e ect of a source resistor on Q-point conditions, solve Problem 4.10 with RS 500  and all else unchanged. Ans: a VGG 3:58 V; b VDSQ 4 V
CHARACTERISTICS OF FIELD-EFFECT TRANSISTORS AND TRIODES
[CHAP. 4
+ VDD RD
RG _ RS _V
Fig. 4-32
Solve Problem 4.12 with a 200- source resistor RS added to the circuit, and all else unchanged. Ans: a R2 190 k; b RD 9:4 R For the n-channel JFET circuit of Fig. 4-20, IDSS 6 mA; Vp0 4 V; RD 5 k; RS 10 k; VDD 15 V, and VSS 10 V. The JFET is described by (4.2). (a) Find the value of VG that renders Vo 0, and (b) determine VDSQ if Vo 0. Ans: a 17:63 V; b 10 V In the di erential ampli er of Fig. 4-22, the identical JFETs are characterized by IDSS 10 mA; Vp0 4 V, and iG 0. If VDD 15 V; VSS 5 V; RS 3 k, and RD 5 k, nd IDQ1 and VDSQ1 . Ans: 1:27 mA, 6.03 V The di erential ampli er of Fig. 4-22 has the circuit element values of Problem 4.37. The identical JFETs are described by the model of Example 4.1. Use SPICE methods to determine voltage vo1 vo2 . (Netlist code available from author website.) Ans: 8:81 V A voltage source is connected to the di erential ampli er of Fig. 4-22 such that VG1 0:5 V. Let VDD 15 V, VSS 2 V; IDSS 10 mA; Vp0 4 V for the identical JFETs, RD 6 k, and RS 1 k. Ans: a 2:53 V; b 8:42 V Find (a) vo1 and (b) vo2 . For the series-connected, nonidentical JFETs of Fig. 4-23, iG1 iG2 0; IDSS1 8 mA; IDSS2 10 mA, and Let VDD 15 V; RG 1 M; RD 5 k, and RS 2 k. Find (a) IDQ1 ; Vp01 Vp02 4 V. (b) VGSQ1 ; c VGSQ2 ; d VDSQ1 , and (e) VDSQ2 . Ans: a 1:22 mA; b 2:44 V; c 2:605 V; d 0:165 V; e 6:295 V The series-connected, identical JFETs of Fig. 4-23 are characterized by IDSS 8 mA; Vp0 4 V, and iG 0:5A. If VDD 15 V; RD 5 k; RS 2 k, and RG 1 M, nd (a) VGSQ1 ; b VGSQ2 , Ans: a 3:44 V; b 3:44 V; c 0 V; d 6:46 V (c) VDSQ1 , and (d) VDSQ2 . In the circuit of Fig. 4-24, the identical JFETs are described by IDSS 8 mA; Vp0 4 V, and iG 0:1 A. If RD 1 k; RS 2 k; RG 1 M, and VDD 15 V, nd (a) VGSQ1 ; b VGSQ2 ; c IDQ2 , (d) VDSQ2 , and (e) VDSQ1 . Ans: a 3:986 V; b 1:65 V; c 2:76 mA; d 6:72 V; (e) 8:37 V For the enhancement-mode MOSFET of Problem 4.20, determine the value of IDon . Ans: 5:6 mA
4.43 4.44
Let VDD 15 V; RD 1 k; RS 500 , and R2 10 k for the circuit of Fig. 4-18. The MOSFET is a depletion enhancement mode device that can be characterized by the parameters of Example 4.2 except that Vto 4 V. Use SPICE methods to determine the range of R1 such that the MOSFET is (a) biased for
CHAP. 4]
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