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PSpice o ers two features that allow direct study of circuit performance change due to parameter variation. The rst of these features is simply called sensitivity analysis. It is invoked by a control statement of the following format: .SENS sensitive variable The sensitive variable can be any node voltage or the current through any independent voltage source. A table is generated in the output le that gives the sensitivity of the sensitive variable to each parameter (speci ed or default) in the model of all BJTs and diodes that are directly comparable with (5.11) and (5.12).
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Example 5.9. For the ampli er of Fig. 5-1, use SPICE methods to determine the sensitivity of ICQ to changes in (a) if RB = ( RE and (b) if RB = ! RE . Bias the transistor such that VCEQ has approximately the same value for both cases.
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(a) The generic npn transistor of Example 3.2 is used. It is not necessary to add the current source ICBO of Fig. 5-1 as the parameter Isc of the transistor model speci es the collector-base leakage current. Set VBB 1 V, VCC 15 V; RB 2 k; RC 5 k, and RE 200 . The netlist code below describes the resulting circuit.
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Ex5_9.CIR VBB 0 1 -1V VCC 0 4 -15V RB 1 2 2kohm RC 3 4 5kohm RE 5 0 200ohm Q 3 2 5 QNPNG .MODEL QNPNG NPN(Is=10fA Ikf=150mA Isc=10fA Bf=150 + Br=3 Rb=1ohm Rc=1ohm Va=75V Cjc=10pF Cje=15pF) .SENS I(VCC) .PRINT DC IC(Q) IB(Q) .END
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Execute hEx5_9.CIRi and examine the output le to nd values for calculation of . Hence, RB 2 103 12:4  ( RB 200  160:8 From the sensitivity output table, nd S 6:127 10 7 A/unit. (b) Edit hEx5_9.CIRi to set VBB 1:32 and RB 35 k. Leave other values unchanged. Execute hEx5_9.CIRi to see that V 3; 5 VCEQ 6:86 V V 3 V 5 from small signal bias solution in output le] which is approximately equal to the value of 6.84 V in part (a). With the same quiescent point, is unchanged and RB 35 103 223:9  > RE 200  156:3 From the sensitivity table in the output le, nd S 4:945 10 6 A/unit. Thus, the sensitivity of ICQ to variation in has increased by a factor of 8 over the case of part (a) where RB = ( RE . I VCC 1:568 10 3 160:8 I VBB 9:751 10 6
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The second PSpice feature for convenient study of circuit performance change due to parameter variation is known as worst-case analysis. It is implemented by a control statement of the following format: .WCASE analysis type sensitive variable YMAX DEVICES device type The analysis type may be ac, dc, or transient as speci ed in the netlist code. The sensitive variable can be any current or voltage. The device type can be any element of the circuit that has a model explicitly appearing in the netlist code. The percentage deviation (DEV) for the parameter of interest must be speci ed within the model parameter list. The worst-case analysis actually calculates the circuit performance at the extremes of operation rather than giving a projected change as results from the sensitivity analysis. Owing to the nonlinear nature of many device parameter changes, the worst-case analysis should be used if other than a small change in the operating point is anticipated to give a better accuracy than would result from sensitivity analysis.
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Example 5.10. For the circuit of Fig. 5-1, let VBB 1:32 V; VCC 15 V; RB 35 k; RC 5 k, and RE 200 . Use the npn transformer of Example 5.9, where the current source ICBO is modeled by the parameter Isc 10 fA. As in part (b) of Example 5.9, the transistor is biased for near-maximum symmetrical swing, but with
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