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iL vds =RL Av Zin 10:35 440 103 325:3 ii vi =Zin RL 14 103
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For the JFET ampli er of Fig. 7-5, gm 2 mS; rds 30 k; RS 3 k; RD RL 2 k; R1 200 k; R2 800 k; and ri 5 k. If CC and CS are large and the ampli er is biased in the pincho region, nd (a) Zin ; b Av vL =vi ; and (c) Ai iL =ii .
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CHAP. 7]
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SMALL-SIGNAL MIDFREQUENCY FET AND TRIODE AMPLIFIERS
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(a) The current-source small-signal equivalent circuit is drawn in Fig. 7-11. Since the gate draws negligible current, Zin RG
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ii +
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R1 R2 200 103 800 103 160 k R1 R2 1000 103
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D id + + gm Lgs rds
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_ _ S _
LL _
Fig. 7-11 (b) By voltage division at the input loop, vgs RG 160 103 vi vi 0:97vi R G r1 165 103 1
The dependent current source drives into Rep , where 1 1 1 1 1 1 1 1 S Rep rds RD RL 30 103 2 103 2 103 967:74 and so Eliminating vgs between (1) and (2) yields Av vL 0:97 gm Rep 0:97 2 10 3 967:74 1:88 vi vL gm vgs Rep (2)
Ai
iL vL =RL A R ri 1:88 165 103 v G 155:1 RL ii vi RG ri 2 103
Show that a small-signal equivalent circuit for the common-drain FET ampli er of Fig. 4-15 is given by Fig. 7-12(b).
The voltage-source model of Fig. 7-1(b) has been inserted in the ac equivalent of Fig. 4-15, and the result redrawn to give the circuit of Fig. 7-12(a), where RG is determined as in Problem 4.6. Voltage vgd , which is
rds m+1
G + Lgs + +
_S +
G + + RG
S id
mLgs RG
+ RS
Lo _ Li
m L m + 1 gd _
+ RS
Lo _
_ rds _ D (a) b
_ _ D (b)
Fig. 7-12
SMALL-SIGNAL MIDFREQUENCY FET AND TRIODE AMPLIFIERS
[CHAP. 7
more easily determined than vgs , has been labeled. With terminals a; b opened in Fig. 7-12(a), KVL around the S; G; D loop yields vgd vgs  1 Then the Thevenin voltage at the open-circuited terminals a; b is  v vTh vgs  1 gd 1
The Thevenin impedance is found as the driving-point impedance to the left through a; b (with vi deactivated or shorted), as seen by a source vab driving current ia into terminal a. Since vgs vab , KVL around the output loop of Fig. 7-12(a) gives vab vgs ia rds vab ia rds v r RTh ab ds ia  1
from which
Expressions (1) and (2) lead directly to the circuit of Fig. 7-12(b).
Figure 7-13(a) is a small-signal equivalent circuit (voltage-source model) of a common-gate JFET ampli er. Use the circuit to verify two rules of impedance and voltage re ection for FET ampli ers: (a) Voltages and impedances in the drain circuit are re ected to the source circuit divided by  1. [Verify this rule by nding the Thevenin equivalent for the circuit to the right of a; a 0 in Fig. 7-13(a) and showing that Fig. 7-13(b) results.] (b) Voltages and impedances in the source circuit are re ected to the drain circuit multiplied by  1. [Verify this rule by nding the Thevenin equivalent for the circuit to the left of b; b 0 in Fig. 7-13(a) and showing that Fig. 7-13(c) results.]
mLgs S _
RS +
id + RD
_ a
Lo _
b (a)
RS +
rds m+1 + RD m+1 ( m + 1) Li _
( m + 1)RS
rds + RD
Lo _
_ (b)
Fig. 7-13 (a) With a; a 0 open, id 0; hence, vgs 0 and vTh 0. After a driving-point source vaa0 is connected to terminals a; a 0 to drive current ia into terminal a, KVL gives vaa 0 vgs ia rds RD 1
CHAP. 7]
SMALL-SIGNAL MIDFREQUENCY FET AND TRIODE AMPLIFIERS
But vgs vaa 0 , which can be substituted into (1) to give RTh vaa 0 r R ds D ia  1  1 2
With vTh 0, insertion of RTh in place of the network to the right of a; a 0 in Fig. 7-13(a) leads directly to Fig. 7-13(b). (b) Applying KVL to the left of b; b 0 in Fig. 7-13(a) with b; b 0 open, while noting that vi vgs , yields vTh vi vgs  1 vi 3 Deactivating (shorting) vi , connecting a driving-point source vbb 0 to terminals b; b 0 to drive current ib into terminal b, noting that vgs ib RS , and applying KVL around the outer loop of Fig. 7-13(a) yield vbb 0 ib rds RS vgs ib rds  1 RS The Thevenin impedance follows from (4) as RTh vbb 0 rds  1 RS ib 5 4
When the Thevenin source of (3) and impedance of (5) are used to replace the network to the left of b; b 0 , the circuit of Fig. 7-13(c) results.
Suppose capacitor CS is removed from the circuit of Problem 7.4 (Fig. 7-5), and all else remains unchanged. Find (a) the voltage-gain ratio Av vL =vi ; b the current-gain ratio Ai iL =ii , and (c) the output impedance Ro looking to the left through the output port with RL removed.
(a) The voltage-source small-signal equivalent circuit is given in Fig. 7-14 (the current-source model was utilized in Problem 7.4). Voltage division and KVL give vgs
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