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The pulse generator, V1, is used as the clock. Because we will generate 256 values in the table, this clock is 256 times greater than the output frequency. Flip- op X1 was created using logic expressions. It latches the data between clock pulses. V2 is a sine wave that is used as a reference in the circuit. R1, R5, C1, and C2 lter the pulse-coded waveform and reconstruct the sine wave. EB1 is a simple comparator that sets the output bit high if the sine-wave output is lower than the sine-wave reference value or sets the output bit low if the sine-wave output is higher than the sine-wave reference value. EB2 shifts the level of the bit values to a zero-one format (if V(3) is greater than 1, then V(9) is set to 1 V; otherwise, V(9) is set to 0 V). The SPICE .FOUR analysis is performed on the sine-wave output in order to place the total harmonic distortion in the output table. The circuit is simulated several times, with different amplitude values for V2. The lowest distortion occurs with the values listed in Fig. 7.1. As we look at the output data, we can see the bit patterns and the sine-wave output at each lter stage. Note that more sophisticated lters could produce lower distortion, as could more values in the data table. Figure 7.2 shows the sine-wave output waveform and the one-zero bit pattern produced by EB2. Note that the circuit starts with zero initial voltage. For this reason, two cycles are simulated and the data for the Fourier analysis are extracted only from the second cycle so that the transient residues are eliminated.
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V(3) Q X1 FFLOP R1 4.7K
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V2 SIN
B1 V=(V(5)-V(7)) > 0 2.5 : -2.5 R4 1MEG
Schematic and netlist showing a novel approach for generating a bit
pattern.
DC-to-AC Conversions
SINE: BIT PATTERN GENERATOR .TRAN 9.766U 9M 0 1U UIC .FOUR 400HZ V(1) .PROBE V(1)=OUT V(3)=Q V(9)=BITS V(7)=FLTR1 .PRINT TRAN V(1) V(3) V(9) V(7) R1 3 7 4.7K C1 7 0 47N IC=0 V1 4 0 PULSE -2.5 2.5 10N 10N 10N 5U 9.766U V2 5 0 SIN 0 1.5 400 R4 5 0 1MEG R5 7 1 47K C2 1 0 8.2N IC=0 EB1 6 0 Value={ IF ( (V(5)-V(7)) > 0 , 2.5 , -2.5 ) } EB2 9 0 Value={ IF ( V(3) > 1 , 1 , 0 ) } X1 4 6 0 0 2 3 FFLOPZero .SUBCKT FFLOPZero 1 2 11 12 5 6 CLK D R S QB Q X1 7 4 2 8 NAND3Z 0 X2 8 3 10 9 NAND3Z 0 X3 1 8 10 7 NAND3Z 1 X4 4 9 1 10 NAND3Z 0 X5 4 7 6 5 NAND3Z 1 X6 5 10 3 6 NAND3Z 0 X7 11 4 INVZ X8 12 3 INVZ .ENDS FFLOPZero .SUBCKT NAND3Z 0 1 2 3 4 E1 5 0 VALUE = { IF ( (V(1)>0) & (V(2)>0) & (V(3)>0), -2.5, 2.5 ) } R1 5 4 400 C1 4 0 20P IC=0 .ENDS NAND3Z 0 .SUBCKT NAND3Z 1 1 2 3 4 E1 5 0 VALUE = { IF ( (V(1)>0) & (V(2)>0) & (V(3)>0), -2.5, 2.5 ) } R1 5 4 400 C1 4 0 20P IC=5 .ENDS NAND3Z 1 .SUBCKT INVZ 1 2 E1 3 0 VALUE = { IF ( V(1)>0, -2.5, 5 ) } R1 3 2 100 C1 2 0 10P IC=5 .ENDS INVZ .END
(Continued )
Seven
BITS in Volts OUT in Volts
Wfm2:
Wfm1:
500M
-500M
500U
1.50M
2.50M
3.50M
4.50M
Time in Secs
Sine-wave output and bit pattern produced by the circuit in Fig. 7.1.
Although this demonstrates the circuit operation, it does not produce the data in a desirable format. A section of the output listing is shown in Fig. 7.3. The distortion analysis results are displayed along with the output data in the output le. To obtain the table in the desired format, we will resimulate a modi ed version of the circuit. The .OPTIONS Numdgt=1 setting causes the output to be displayed in the output le using no decimal places. Only one column of data will appear in the output le. The column is the bit pattern. The numbers are displayed in the exponential format. Via the search and replace command found in most text editors, we can clean up the two values that are present. Replace 1e+000 with 1, and replace 0e+000 with 0. The result will be a bit pattern, as shown in the partial output le in Fig. 7.4. The left column is our bit pattern (which has 256 values) and the right column is the index (think of the index as an address ranging from 0 to 255). This bit pattern can now be coded into ROM. To achieve a three-phase bit pattern, the circuit can be copied three times and the sine-wave reference can be replaced by a three-phase reference. The result will be three columns of bit data and an index column. State Machine Modeling in XSPICE Some SPICE simulators have the ability to model digital functions by using a state machine model (see chap. 8). State machine models allow