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to accomplish this task. The time step is increased after the event, until the next cycle, when it is again reduced. This time step hysteresis can cause an excessive number of unnecessary calculations. To correct this problem, we can regress to a SPICE 2 methodology and force the simulator to have a xed time step value. To force the time step to be a xed value, set the TRTOL value to 25, i.e., .OPTIONS TRTOL =25. The default value is 7. The Trtol parameter controls how far ahead in time SPICE tries to jump. The value of 25 causes PSpice to try to jump far ahead. Then set TMAX (maximum allowed time step) in the .TRAN statement to a value that is between 1/10 and 1/100 of the switching cycle period. This has the opposite effect; it forces the time step to be limited. Together, they effectively lock the simulator time step to a value that is between 1/10 and 1/100 of the switching cycle period and eliminate virtually all of the rejected time points. These settings can result in over a 100% increase in speed! Note: In order to verify the number of accepted and rejected time points, you may issue the .OPTIONS ACCT parameter and view the summary data at the end of the output le. If this does not help the simulation converge, proceed to the next section that has more details. Simulation Convergence The answer to a nonlinear problem, such as those in the SPICE DC and transient analyses, is found via an iterative solution. For example, PSpice makes an initial guess at the circuit s node voltages and then, using the circuit conductances, calculates the mesh currents. The currents are then used to recalculate the node voltages, and the cycle begins again. This continues until all the node voltages settle to values that are within speci c tolerance limits. These limits can be altered using various .OPTIONS parameters such as RELTOL, VNTOL, and ABSTOL. If the node voltages do not settle down within a certain number of iterations, the DC analysis will issue an error message such as No convergence in DC analysis, Singular matrix, GMIN stepping failed, or Source stepping failed. PSpice will then halt the run because both the AC and transient analyses require an initial stable operating point in order to proceed. During the transient analysis, this iterative process is repeated for each individual time step. If the node voltages do not settle down, the time step is reduced and PSpice tries again to determine the node voltages. If the time step is reduced beyond a speci c fraction of the total analysis time, the transient analysis will issue the error message Time step too small, and the analysis will be halted. Convergence problems come in all shapes, sizes, and disguises, but they are usually related to one of the following:
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Solving Convergence and Other Simulation Problems
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Circuit topology Device modeling Simulator setup The DC analysis may fail to converge because of incorrect initial voltage estimates, model discontinuities, unstable/bistable operation, or unrealistic circuit impedances. Transient analysis failures are usually due to model discontinuities or unrealistic circuit, source, or parasitic modeling. In general, you will have problems if the impedances, or impedance changes, do not remain reasonable. Convergence problems will result if the impedances in your circuit are too high or too low. The various solutions to convergence problems fall under one of two types. Some are simply band aids that merely attempt to x the symptom by adjusting the simulator options. Other solutions actually affect the true cause of the convergence problems. The following techniques can be used to solve a majority of convergence problems. When a convergence problem is encountered, you should start at solution 0 and proceed with the subsequent suggestions until convergence is achieved. The sequence of the suggestions is structured so that they can be incrementally added to the simulation. The sequence is also de ned so that the initial suggestions will be of the most bene t. Note that suggestions that involve simulation options may simply mask the underlying circuit instabilities. Invariably, you will nd that once the circuit is properly modeled, many of the options xes will no longer be required! General Discussion Many power electronics convergence problems can be solved with the .OPTIONS GMIN parameter. GMIN is the minimum conductance across all semiconductor junctions. The conductance is used to keep the matrix well conditioned. Its default value is 1E-12 mhos. Setting GMIN to a value between 1n and 10n will often solve convergence problems. Setting GMIN to a value greater than 10n may cause convergence problems. GMIN stepping is an algorithm in PSpice and SPICE 3 that greatly improves DC convergence. This algorithm uses a constant minimal junction conductance that keeps the sparse matrix well conditioned and a separate variable conductance to ground at each node, which serves as a DC convergence aid. The variable conductances cause the solution to converge more quickly. They are then reduced, and the solution is recomputed. The solution is eventually found with a suf ciently small conductance. Then the conductance is removed entirely in order to
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