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Use a reasonable rise time in the PULSE statement to simulate realistic turn on. For example,
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V1 1 0 PULSE 0 5 0 1U
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will provide a 5-V supply with a turn-on time of 1 s. The rst value after 5 (in this case, 0) is the turn-on delay, which can be used to allow the circuit to stabilize before the power supply is applied. 5. Add UIC (use initial conditions) to the .TRAN statement. Example: .TRAN .1N 100N UIC Insert the UIC (use initial conditions) keyword in the .TRAN statement. UIC will cause PSpice to completely bypass the DC analysis. You should add any applicable .IC and IC (initial conditions) statements to assist in the initial stages of the transient analysis. Be careful when you set initial conditions, for a poor setting may cause convergence dif culties. AC analysis note: Solutions 4 and 5 should be used only as a last resort, because they will not produce a valid DC operating point for the circuit (all supplies may not be turned on and circuit may not be properly biased). Therefore, you cannot use solutions 4 and 5 if you want to perform an AC analysis, because the AC analysis must be preceded by a valid operating point solution. However, if your goal is to proceed to the transient analysis, then solutions 4 and 5 may help you and may possibly uncover the hidden problems that plague the DC analysis.
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Transient Convergence Solutions 0. Check circuit topology and connectivity. This item is the same as item 0 in the DC analysis. 1. Set RELTOL=0.01 or 0.005 in the .OPTIONS statement. Example: .OPTIONS RELTOL=0.01 This option is encouraged for most simulations, because reducing RELTOL can increase the simulation speed by 10% to 50%. Only a minor loss in accuracy usually results. A useful recommendation is to set RELTOL to 0.01 for initial simulations and then reset it to its default value of 0.001 when you have the simulation running the way you like it and a more accurate answer is required. Setting RELTOL to a value less than 0.001 is generally not required. 2. Set ITL4=500 in the .OPTIONS statement. Example: .OPTIONS ITL4=500
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This increases the number of transient iterations that SPICE will attempt at each time point before it gives up. Values that are greater than 500 or 1000 will not usually bring convergence. 3. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it. Example: . OPTION ABSTOL=1N VNTOL=1M ABSTOL and VNTOL should be set to about 8 orders of magnitude below the level of the maximum voltage and current. The default values are ABSTOL=1p and VNTOL=1 . These values are generally associated with IC designs. 4. Realistically model your circuit; add parasitics, especially stray/junction capacitance. The idea here is to smooth any strong nonlinearities or discontinuities. This may be accomplished via the addition of capacitance to various nodes and verifying that all semiconductor junctions have capacitance. Other tips include the following: Use RC snubbers around diodes. Add capacitance for all semiconductor junctions (3 pF for diodes and 5 pF for BJTs if no speci c value is known). Add realistic circuit and element parasitics. Watch the real-time waveform display and look for waveforms that transition vertically (up or down) at the point during which the analysis halts. These are the key nodes that you should examine for problems. If the .MODEL de nition for the part does not re ect the behavior of the device, use a subcircuit representation. This is especially important for RF and power devices such as RF BJTs and power MOSFETs. Many model vendors cheat and try to force t the SPICE .MODEL statement in order to represent a device s behavior. This is a sure sign that the vendor has skimped on quality in favor of quantity. Primitive level 1 or 3 .MODEL statements cannot be used to model most devices above 200 MHz because of the effect of package parasitics. And .MODEL statements cannot be used to model most power devices because of their extreme nonlinear behavior. In particular, if your vendor uses a .MODEL statement to model a power MOSFET, throw away the model. It is almost certainly useless for transient analysis. 5. Reduce the rise/fall times of the PULSE sources. Example: VCC 1 0 PULSE 0 1 0 0 0 becomes VCC 1 0 PULSE 0 1 0 1U 1U Again, we are trying to smooth strong nonlinearities. The pulse times should be realistic, not ideal. If no rise or fall time values are given,
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