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Common Gate Circuit
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In the common gate circuit (Fig. 23-12), the gate is placed at signal ground. The input is applied to the source. The illustration shows an N-channel JFET. For other types of FETs, the same considerations apply as previously described for the common source circuit. Enhancement-mode devices would require a resistor between the gate and the positive supply terminal (or the negative terminal if the MOSFET is P-channel). The dc bias for the common gate circuit is basically the same as that for the common source arrangement. But the signal follows a different path. The ac input signal enters through C1. Resistor R1 keeps the input from being shorted to ground. Gate bias is provided by R1 and R2. Capacitor
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23-12 Common gate configuration. This diagram shows an N-channel
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JFET circuit.
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Common Drain Circuit 375
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C 2 places the gate at signal ground. In some common gate circuits, the gate is directly grounded, and R2 and C 2 are not necessary. The output signal leaves the circuit through C3. Resistor R3 keeps the output signal from being shorted through the power supply. The common gate arrangement produces less gain than its common source counterpart. But a common gate amplifier is not likely to break into unwanted oscillation, making it a good choice for power-amplifier circuits, especially at RF. The output is in phase with the input.
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Common Drain Circuit
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A common drain circuit is shown in Fig. 23-13. In this circuit, the collector is at signal ground. It is sometimes called a source follower. The FET is biased in the same way as for the common source and common gate circuits. In the illustration, an N-channel JFET is shown, but any other kind of FET could be used, reversing the polarity for P-channel devices. Enhancement-mode MOSFETs would need a resistor between the gate and the positive supply terminal (or the negative terminal if the MOSFET is P-channel). The input signal passes through C 2 to the gate. Resistors R1 and R2 provide gate bias. Resistor R3 limits the current. Capacitor C3 keeps the drain at signal ground. Fluctuating dc (the channel current) flows through R1 as a result of the input signal; this causes a fluctuating dc voltage to appear across R1. The output is taken from the source, and its ac component passes through C1. The output of the common drain circuit is in phase with the input. This scheme is the FET analog of the bipolar common collector arrangement. The output impedance is rather low, making this circuit a good choice for broadband impedance matching.
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23-13 Common drain configuration, also known as a source follower. This
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diagram shows an N-channel JFET circuit.
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376 The Field Effect Transistor
Quiz
Refer to the text in this chapter if necessary. A good score is at least 18 correct. Answers are in the back of the book. 1. The current through the channel of a JFET is directly affected by all of the following, except the (a) drain voltage. (b) transconductance. (c) gate voltage. (d) gate bias. 2. In an N-channel JFET, pinchoff occurs when the gate bias is (a) small and positive. (b) zero. (c) small and negative. (d) large and negative. 3. The current consists mainly of holes when a JFET (a) has a P-type channel. (b) is forward-biased. (c) is zero-biased. (d) is reverse-biased. 4. A JFET might work better than a bipolar transistor in (a) a high-voltage rectifier. (b) a weak-signal RF amplifier. (c) a power-supply filter. (d) a power transformer. 5. In a P-channel JFET, (a) the drain is forward-biased. (b) the source-gate junction is forward-biased. (c) the drain is negative relative to the source. (d) the gate must be at dc ground. 6. A JFET is sometimes biased at or beyond pinchoff in (a) a power amplifier. (b) a rectifier. (c) a filter. (d) a weak-signal amplifier. 7. The gate of a JFET exhibits a (a) forward bias. (b) high impedance.
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